strahd_von_zarovich
Advanced Member level 4
Hi everyone,
I am trying to design a reference clock section for my PLL ICs and FPGA. I have a TCXO with 10MHz output ( DOT050F). The problem is it has only 4mA output drive current. Therefore I am planning to use a buffer(5PB1102) and amplifier (GALI-55+). Here is my block schematic.
There are couple of questions I want to ask,
1- TCXO's output characteristic is 15pF, buffer's input capacitance is 5pF , Does a 10pF capacitor parallel to buffer's input result a better matching ?
2- Buffer has a LVCMOS output. Would it be a problem for RF amplifiers like GALI-55+. (I am going to use an AC-coupling capacitor for amplifier's input.)
3- I have researched some schematics for reference clock sections and resistive power dividers are generally used. What is the main reason for this? Is it because it is a cheap way to power divide?
4- Buffer has 2.4V output high voltage at 3.3V Vdd according to the datasheet. Does that mean it has ~17dBm output power :shock: .
Thanks in advance.
I am trying to design a reference clock section for my PLL ICs and FPGA. I have a TCXO with 10MHz output ( DOT050F). The problem is it has only 4mA output drive current. Therefore I am planning to use a buffer(5PB1102) and amplifier (GALI-55+). Here is my block schematic.
There are couple of questions I want to ask,
1- TCXO's output characteristic is 15pF, buffer's input capacitance is 5pF , Does a 10pF capacitor parallel to buffer's input result a better matching ?
2- Buffer has a LVCMOS output. Would it be a problem for RF amplifiers like GALI-55+. (I am going to use an AC-coupling capacitor for amplifier's input.)
3- I have researched some schematics for reference clock sections and resistive power dividers are generally used. What is the main reason for this? Is it because it is a cheap way to power divide?
4- Buffer has 2.4V output high voltage at 3.3V Vdd according to the datasheet. Does that mean it has ~17dBm output power :shock: .
Thanks in advance.