buenos
Advanced Member level 3
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- Oct 24, 2005
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until now, i was doing both, full projects.
I got a job offer, where i have to chose (i applied to the hw-eng position, not to the layout eng). So, now, I am thinking in accepting the offer as a hw-engineer. I asked them about if i can do both, but they said: no.
I am afraid, that I have a lot of everyday practice-knowledge about layout design, but if i am not using it in practice, after few years, me knowledge decays and will not be accurate anymore.
I know, i have to understand the manufacturing process, i do, i did myself in my early projects (in the SMD lab at the university with proper equipment, also for BGAs to get the knowledge for next designs...), but i think the layout is more difficoult than the things what i want to know about manuf., so easier to forget.
If the layout engineer does something wrong, it would be hard for me to fix it in the layout, because i dont know, where he has routed the traces...
who does the signal integrity simulations and the pre/post-layout timing analysis?
who simulates for power delivery and decoupling network design?
who sets up the constraints in the layout tool? (there are more difficoult rules too, like in the cadence allegro: the custom measurements)
who determines the stackup, the impedance-calculations, and the bus-to-layer-assigments?
who simulates for the loss-budget for PCI-express serial lines?
and who earns more, the hardware (sch) designer, or the layout engineer?
I got a job offer, where i have to chose (i applied to the hw-eng position, not to the layout eng). So, now, I am thinking in accepting the offer as a hw-engineer. I asked them about if i can do both, but they said: no.
I am afraid, that I have a lot of everyday practice-knowledge about layout design, but if i am not using it in practice, after few years, me knowledge decays and will not be accurate anymore.
I know, i have to understand the manufacturing process, i do, i did myself in my early projects (in the SMD lab at the university with proper equipment, also for BGAs to get the knowledge for next designs...), but i think the layout is more difficoult than the things what i want to know about manuf., so easier to forget.
If the layout engineer does something wrong, it would be hard for me to fix it in the layout, because i dont know, where he has routed the traces...
who does the signal integrity simulations and the pre/post-layout timing analysis?
who simulates for power delivery and decoupling network design?
who sets up the constraints in the layout tool? (there are more difficoult rules too, like in the cadence allegro: the custom measurements)
who determines the stackup, the impedance-calculations, and the bus-to-layer-assigments?
who simulates for the loss-budget for PCI-express serial lines?
and who earns more, the hardware (sch) designer, or the layout engineer?