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PKS was the first physical synthesis tool even before Physical Compiler (PC) and magma. The tool could do floorplan, some elementary power routing, full legal placement and global routing (all timing driven) in addition to RTL logic synthesis just like synopsys' DC. The 5.xx version had powerful datapath features like operator merging, complex arithemetic designware components (just like DC) and also power optimization features. However since the backend was done in a flat fashion in PKS, the size of the design (especially after half a million gates) constrained its usage. Realizing that most of the designs were going in the multimillion gates, Cadence introduced SOC encounter (this tool was called 'first encounter' before its purchase from Silicon Perspectives by Cadence). Cadence also decided to stop PKS since there was a lot of overlap between SOC-E and PKS. Basically SOC-E is much better in the back-end compared to PKS. The older versions 3.3, 3.4 were not good for timing driven optimizations (compared to PKS), so PKS was bundled into SOC-E so that the optimization rich features of PKS could be exploited by a designer in a opportunistic manner. Hope this helps.
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