Do the corner of different devices in tsmc has some relationship

[easyads]

Hi ,all
The following question is about tsmc 0.13um RF process
1. Do the corner of core device and IO device has some relationship? For example, if nmos1v goes to "tt" corner, then nmos3v will also go to "tt" corner? Or the nmos1v and nmos3v's corner has no correlation?
2. Please describe the corner relationship between mos_var and core device "nmos1v, pmos1v". For example, if nmos1v goes to "ss" corner, then mos_var will also go to "ss" corner ?
3.Please describe the corner relationship between bjt devices "vpnp, npn" and core device "nmos1v, pmos1v". For example, if nmos1v goes to "ss" corner, then vpnp will also go to "ss" corner ?
4. Please describe the corner relationship between diode devices "diodep,dioden" and core device "nmos1v, pmos1v". For example, if nmos1v goes to "ss" corner, then diodep will also go to "ss" corner ?
5. Please describe the corner relationship between rphpoly and rphriply; between rphpoly and rnhpoly; between rphpoly and rplpoly. For example, if rphpoly goes to "ss" corner, then rphripoly will also go to "ss" corner ?

Thank you.

 

[erikl]

Usually corner conditions are valid for all devices.

 

[Teddy]

a) - open to model file and read through it!!!! Also open the little text file which shows how to use tsmc models.
b) tsmc usua;ly provides libraries for core and io (1V and 3V) devices separately. That means in simulations if you want to change all of them to ss you have to change corner for each of them separately.
Usualy the (in case of spectre) call for typical model of core devices would look like ..... section=tt and for the io section=tt_3v or similar. The same it is for bipolars and resistors and so on.
That said you can simulate with core devices set to ss and ios to ff and bipolars can be tt..... That depends how you setup your simulation corners.

Now the reality is a bit different - each model was extracted with typical silicon wafer and each device had its own ideal structure probably NMOS had multiple separate NMOS structures with different W and L. Corners are then most of the time calculated. Does NMOS in ss affect PMOS or bipolar - yes it can. If the diffusions are not right sure. But how and what are the exact relations? - that I bet even tsmc process / modelling guys will not tell.

If you have good set of montecarlo models (and not only covering MOS devices) then run MC

- - - Updated - - -

a) - open to model file and read through it!!!! Also open the little text file which shows how to use tsmc models.
b) tsmc usua;ly provides libraries for core and io (1V and 3V) devices separately. That means in simulations if you want to change all of them to ss you have to change corner for each of them separately.
Usualy the (in case of spectre) call for typical model of core devices would look like ..... section=tt and for the io section=tt_3v or similar. The same it is for bipolars and resistors and so on.
That said you can simulate with core devices set to ss and ios to ff and bipolars can be tt..... That depends how you setup your simulation corners.

Now the reality is a bit different - each model was extracted with typical silicon wafer and each device had its own ideal structure probably NMOS had multiple separate NMOS structures with different W and L. Corners are then most of the time calculated. Does NMOS in ss affect PMOS or bipolar - yes it can. If the diffusions are not right sure. But how and what are the exact relations? - that I bet even tsmc process / modelling guys will not tell.

If you have good set of montecarlo models (and not only covering MOS devices) then run MC