Do the chips reserve the pins that can access its scan chain (if have)

[zhengyudennis]

Hi all,
Sorry to bother you. Do the manufactured chips (such as the micro-processor) on the market reserve the pins that can access their scan chains (e.g. input the data into the scan chain or shift out the responses), if such chips adopt scan-chain technique for DFT? Thanks very much for the replies.

Best,
Dennis

 

[maulin sheth]

Yes. For DFT, chip reserves the scan in,scan out, scan enable pin which are only used at the time of test mode not use in functionality mode.
This is also one of the overhead of scan insertion DFT technique.

 

[zhengyudennis]

Yes. For DFT, chip reserves the scan in,scan out, scan enable pin which are only used at the time of test mode not use in functionality mode.
This is also one of the overhead of scan insertion DFT technique.

I have referred to some chip manuals, but failed to find the pin descriptions for the scan chain. If possible, can you give me an example? Thanks very much for your help.

 

[maulin sheth]

I have also checked the pin level description of chip, that include the scan in-out pins.depends on number of scan chains.

These DFT pins are used only at ATE, not for functional mode.so also check in manual that,the total number of pins after DFT insertion is exact equal to the number of pins in that manual.

Now in some cases, DFT engineer also used the common pins means that pins are used for function and as well as test mode. because both(function and test modes) are never on at same time.