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I feel you have something very wrong here. Your output codes should be very close to your input line. Are you using an ideal DAC to sample your digital codes back into analog for the comparison? If so make sure your DAC is not clocked and works instantly, or you could also slow down your ramp to make sure you don't have a clocking problem. The clocking would add a delay which would make your INL or DNL look alot worse then it should look if the ramp is too fast!
Jgk
You have 28 codes in your output staircase and therefore 4 missing codes. The step size varies quite a bit between the bottom and the top. Is this a commercial ADC or something you designed? If it is a commercial ADC you are probably not setting it up correctly. If it is your design, start with probing the reference ladder (one of the major sources of non-linearity in flash ADC), if the voltage taps are equidistant then look at the bubble correction logic (simple) then comparators (dynamic offset is one of the main issues).
For more information you will have to share more about the design.
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