DLL bias voltage unstable when adding capacitor

[shanmei]

My DLL input signal is 100MHz (10nS), and it has ten delay stages, with each stage delays 1nS. The delay stage is a basic current starving architecture with a pmos and nmos current source to control the current.

The top architecture is shown in the bellowing figure:



The control voltage at Vc, VBP, and VBN are shown in the bellowing figure:



I want to reduce the spikes at VBP and VBN, so I add a 10pF capacitor on node VBP and VBN respectively, but the control voltage starts to oscillate as shown in the bellowing figure. Then I changed the 10 pF capacitor filter to low pass filter (a 10kHz resisor and a 10pF capacitor), which still presents big swing on the control nodes.




I have several questions:

1. Why it is oscillating by adding a capacitor on the bias nodes?
2. Should the DLL be unconditional stable?
3. If it is not unconditional stable, what should I to to prevent oscillation? Any formula to design those parameters?

Thanks.

 

[deba_fire]

You have a type 2 system. With one integrator from charge pump and the other from VCO. You need to add a zero. Place a resistor in series with capacitor after the charge pump. The zero location should be within the unity gain bandwidth of your open loop response.

 

[shanmei]

Thanks. It is DLL, not PLL, no VCO in the loop, so I think there is one integrator from the charge pump and loop filter.

 

[dick_freebird]

There was one, until you added those shunt caps to
the current mirrors for VBN/VBP. Now you have two.
Or really, three (but VPB, 2 and VBN, 3). So your
P and N currents can go out of whack when slewing,
and the DLL & phase detector have to chase that
and bring it back around (perhaps late, perhaps never).