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division core problem, not generating remainder and fractional at all

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dksagra

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hello,

when i am generating division core ..this particular warning is oming..

WARNING:sim:471 - The chosen IP does not support a VHDL behavioral model, generating a VHDL structural model instead.

WARNING:sim:472 - The chosen IP does not support a Verilog behavioral model, generating a Verilog structural model instead.

because of this warning, division core is not producing any remainder and fractional..

please help me..

regards,
 

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