divide the clock frequency by 2

[Shanthanayaki]

Hi all.

Can anyone tell a way to design a circuit that can divide the clock frequency by 2.
I am using XOR gate but cannot get it right.

Shantha

 

[flatulent]

The foolproof way is to have a memory element. Take a D flip flop and feed the Qnot to the D input. Clock it from your original clock source. Q will be at half the frequency.

 

[Shanthanayaki]

Hi,
But that is the clk divider by 2, and the frequency is divide by 2. We want here the frequency multiplier right. Somehow I am confused between the 2 circuits.
Shantha

Added after 19 minutes:

Hi,
I am sorry, I rephrase the question, simple circuit based on combinational logic to double the output frequency.
Shantha

 

[teteamigo]

With EXOR and inverter chain to make a delay


----Delay(1/4*original period)---- input 1 EXOR
--------------------your signal------ input 2 EXOR

 

[flatulent]

There are two dangers to avoid.

One is the minimum required new clock pulse width being violated by your circuit. The delay element controls this width. If you are making a board type design you can use LC delay lines for this function.

The other is that your original clock should be a square wave. Otherwise the new clock pulses will not be uniformly spaced. Unequal spacing can cause problems.

 

[maksya]

A simple T-type (count) trigger divide input frequency by 2 !

 

[mdeepamenon]

why dont you try some frequency multiplier circuits using PLL ic.

 

[sree205]

this entire thing about using a combo block to multiply the frequency is a myth. nobody in real-world uses these circuits.

 

[xihushui]

flatulent:One is the minimum required new clock pulse width being violated by your circuit. The delay element controls this width. If you are making a board type design you can use LC delay lines for this function.
i can't understand it very well.could you explain it particular?

 

[teteamigo]

Delay of signal ---> Like Group delay--> d phase/dw of a filter/system

 

[energeticdin]

Hi
I am Dinesh. I am new member.
For doubling the frquency
module freq_doub(q,clk);

input clk;
output q;

not #5 (o1, clk); (1/4 of clk)== delay
not #5 (o2,o1);

xor(q,o2,clk);

endmodule

 

[neils_arm_strong]

A D flipflop with Qbar fed back to input will serve as a frequency divider.
fout=fin/2.

 

[ouahhabi5]

use a D filpflop and connect the previous clock on tne flipflop's clock the inout D is feedback by Qbar. the new clock is Q

 

[zhangpengyu]

filpflop is must to be used.

 

[ray123]

using flop can avoid the glitch.

 

[shwoo]

The problem is the original poster, Shantha, probably wanted a frequency
doubler, but he posted "divide by 2". That caused a lot of confusion.
Shantha, please make yourself clear. I assume you want to double
the frequency, not divide.
Regards,
S. H.

 

[shankarmit]

In real time for multiplying frequency use pll .. thats the better way to multiply the frequency....

 

[funster]

always @(posedge clk or negedge rst_n) begin
if (~rst_n)
clk_div2 <= #1 1'b0;
else
clk_div2 <= #1 ~clk_div2;
end


best regards

Hi all.

Can anyone tell a way to design a circuit that can divide the clock frequency by 2.
I am using XOR gate but cannot get it right.

Shantha