Divide CLK by 32 : What's best for backend ?

[omara007]

Hi guys ..

If I want to divide my clock frequency by 32 and generate another clock out of that .. what's the best way to do that keeping problems away from timing guys and backend guys ? ..

P.S. I am a front-end guy ..

 

[jarodz]

The easy and straight way is to use a counter to generate the clock signal.

Sincerely,
Jarod

 

[omara007]

what about delayes due to using big counter like a 6-bit counter for example ? .. will it result in any timing problems for the backend guys ? ..

 

[armer]

The delay is only CK->Q, it's small.
I think there are no impact for the layout and timing. In the backend design.

####
/32
CLK -------> CLK32

If there are timing talk between CLK and CLK32, the backend engineer
would match the insertion delay for CLK&CLK32.

 

[beckchm]

In my opinion, your design is not complicated .

So you need not consider too much about the backend.

 

[ami]

Hi omara007
1.If your clock frequency (need to be divided by 32) is low (for an example:155MHz), just use a normal 6 bit counter, it will be OK.

2.If your clock frequency is high (for an example:1.25GHz), it will be another case
* first, divided your clock by 2 (use 1 FFs), you get clk A/2
* continue to divide clock A/2 by 2 (use 1 FF clock by A/s), you get clk A/4
* and so on ....
* at clk A/n (you must minimize the "n" divide by 2), if you think that clock is enough to use counter, use a counter to divide that clock ( ex: at clk A/4, you need a 4bit counter to have a clock A/32)

Regards

 

[jackson_peng]

in my opinion, the timing issue won't be key problem for backend guys. what really care is that when you use both the original clock and divided clock in your system. it will be a problem to do the CTS when you use the counter style clock divider

 

[omara007]

in my opinion, the timing issue won't be key problem for backend guys. what really care is that when you use both the original clock and divided clock in your system. it will be a problem to do the CTS when you use the counter style clock divider

is there any style other than using counter ?

 

[ami]

in my opinion, the timing issue won't be key problem for backend guys. what really care is that when you use both the original clock and divided clock in your system. it will be a problem to do the CTS when you use the counter style clock divider

Hi jackson_peng,
I dont think that using a counter style clock divider will be a problem. Because with a few of FFs of this counter, you can take care the clock drive/balance by hand, CTS insertion is unnecessary here.(only insert CTS at the clk/32 output)
Regards

Added after 7 minutes:

in my opinion, the timing issue won't be key problem for backend guys. what really care is that when you use both the original clock and divided clock in your system. it will be a problem to do the CTS when you use the counter style clock divider

is there any style other than using counter ?

As I have mentioned above, you can use the divide-by-2 circuit. if you need to divide by 32, just use a set aof 5 serialized divide-by-2.
This is a sample of divide-by-2

module CKDIV2
    (
     RSTB,
     CKI,
     CKO
     );

input   RSTB;
input   CKI;
output  CKO;

wire    NOTCKO;
INV     NOTCKOi(.A(CKO),.Y(NOTCKO));
BUF     NOTCKO_BUF1i(.A(NOTCKO),.Y(NOTCKO_BUF1));
DFF     DIV2FFi
    (
     .D(NOTCKO_BUF1),
     .CK(CKI),
     .RST_(RSTB),
     .Q(CKO)
     );                     
endmodule

 

[jackson_peng]

let me say it clear.

The problem in CTS doesn't exist in the clock counter, but it does affact the clock skew of the whole chip, when you use both these two clocks in your system.

It would be difficult to balance the clock skew between orignal clock and the divided clock, because the divided clock is root from the DFF/Q, which could fool the existing EDA tools for CTS.

any further question is welcome.

 

[omara007]

let me say it clear.

The problem in CTS doesn't exist in the clock counter, but it does affact the clock skew of the whole chip, when you use both these two clocks in your system.

It would be difficult to balance the clock skew between orignal clock and the divided clock, because the divided clock is root from the DFF/Q, which could fool the existing EDA tools for CTS.

any further question is welcome.

so , isn't there anyway to make both clocks 100% synchronous and skew-balanced ?

 

[ami]

let me say it clear.

The problem in CTS doesn't exist in the clock counter, but it does affact the clock skew of the whole chip, when you use both these two clocks in your system.

It would be difficult to balance the clock skew between orignal clock and the divided clock, because the divided clock is root from the DFF/Q, which could fool the existing EDA tools for CTS.

any further question is welcome.

OK. but why do you need these 2 clocks skew-balanced? They are 2 separate clock-domains and I think you should consider them as 2 asynchronous clocks (except in the case of a CLK and CLK/2). I have do many of this and I have no complaint from back-end engineer about this.
Regards

 

[jackson_peng]

Treate them as async clock domain means you have to waste the communiation efficiency since synchronous logic is added.

actually, there are also other sytles of clock divider. for example, the gating style clock divider, which can keep the rising edge actually with no skew. but it can't achieve the 50-50 duty cycle. so in this style, the using of fall edge of the divided clock is not allowed.

 

[ami]

OK. But in ASIC design, asynchronous method for data communication between 2 clock-domains will be more reliable and easy to design (especially in this case, 1 fast clock, and 1 slow clock divided). Why must we troulbe ourself in synchronization when there still another better choice
(in some exception, when the clock quatlity is the most important thing, your idea is preferable).

 

[omara007]

Treate them as async clock domain means you have to waste the communiation efficiency since synchronous logic is added..

What do you mean by "wasting the communication efficiency" ? and what is the synchronous logic that u mean ?

actually, there are also other sytles of clock divider. for example, the gating style clock divider, which can keep the rising edge actually with no skew. but it can't achieve the 50-50 duty cycle. so in this style, the using of fall edge of the divided clock is not allowed.

Good idea .. I only use rising edge .. but what makes someone goes for this solution other than synchronizing the rising edge ?
and anymore information about : the gating style clock divider ?

 

[jackson_peng]

I'm sorry to say, that the inter-domain communication has never been reliable or efficient. To avoid metastability, two stage flip-flops has to be bulid on the receiver. To avoid data missing or overtaken, hand shake protocol and data locking has to be added. To improve the efficiency, FIFO sytle communication is needed.

So, it not a good idea to treate the clocks from the same root as asynchronous one.

To omara007:
the gating style divider include two parts: a counter, and a clock gating cell. in this structure, the orignal clock only pass the AND cell to generate the divided clock.

 

[ami]

The question is

Divide CLK by 32 : What's best for backend ?

----> if the two synchronous clocks go round the die, it 's hard for the backend to balance these 2 clocks.