capitan
Newbie level 5
Hello everyone!
I'm having a problem with the behavioral simulation of a single port distributed ram component in isim. It appears that the output of the ram is not clock accurate, but comes 100ps after the clk rising edge . The thing that confuses me is that the output is registered...
I'm using Xilinx 12.1 along with isim. Possibly a tool bug?
**broken link removed**
ps: please ignore all the other signals. Only clk and everything under nnet_mem1 are relevant
I'm having a problem with the behavioral simulation of a single port distributed ram component in isim. It appears that the output of the ram is not clock accurate, but comes 100ps after the clk rising edge . The thing that confuses me is that the output is registered...
I'm using Xilinx 12.1 along with isim. Possibly a tool bug?
**broken link removed**
ps: please ignore all the other signals. Only clk and everything under nnet_mem1 are relevant