Discrete component schematic of a gate driver circuit

[santom]

gate drive circuit

Hi all,
Can anyone teach me the possible operation of the gate driver schematic(not a ready made IC please..!) for a full bridge converter(H bridge) by means of a clear schematic.

It would really be great if anyone can do that here.It would be helpful to so many people as I have seen so many threads realted to this..

Also possibly explain the concepts Dead time generator,Level shifter in the whole power amplifier stage of the class-D amplifier...

Detailed responses are very much apprecialble ..Thanks in advance


Santom

 

[FvM]

discrete gate driver

The aspect of a discrete level shifter and bootstrap circuit has been covered in a circuit example I gave in a previous discussion.

You may want to to replace the 4069 CMOS inverter by a one transistor inverter followed by a complementary common collector output stage as you apparently intend not to use any IC. The shown circuit also has an implicite dead-time generation made up by the LM324 slew-rate and thresholds of both drivers. But it's a specific solution and shouldn't be suggested for general usage.

The basic dead-time generator purpose is to prevent bridge shorts, in other words, turning on both output switches at the same time. Propagation times of driver and output transistor switching times have to be considered for optimal dead-time adjustment.

Not using high-side driver ICs also means giving up additional features of these parts, e.g. low voltage lockout, that can be important to protect the switching transistor from dangerous operation conditions.

However, I also understand Audioguru's comment on the same discussion.

These same questions are on so many websites that I lost count.

Apart from countless forum discussions, there are also power electronics text books covering the topic.

 

[santom]

gate driver circuit

Hi FvM,
Thanks for the reply.But as I said earlier, I couldnt understand the exact working of the driver circuit which you proposed in the earlier discussion topic.Since you propsed this driver circuit, it could be interesting for you to explain about its operation in detail.Can you do that possibly...

Also I have two comparators giving the respective positive and negative values which can be used as inputs to the respective drivers.

If you take some of your valuable time to explain that, it would be helpful to many people in this community.

Thanks in advance.

Santom

 

[FvM]

gate driver schematic

PWM generation (e.g. using triangle function, a target value which is possibly a sine function and a comparator) is a different topic. It doesn't make sense to mix it with driver problems to my opinion. The quoted thread also mixed it cause the author intended a simple pwm reference design. But basically they are different.

In this view, the input to the power stage is a digital signal that sets the output to either high or low. You may alternatively provide individual control signals for low- and high side switch, allowing also a third all off and a forbidden both on (bridge short) state. For a H-bridge that has only high or low state in normal operation, I prefer the first variant, at least in a principal description.

Assuming a digital input signal to the driver, I see these individual functions.

1. The dead time generator is a selective delay that achieves immediate off and delayed on control for both bridge halves. There are different ways to generate it, e.g. monoflops or RCD circuits. After the delay generator, you have individual HIN and LIN control signals.

2. While the LIN signal is usually referenced to low side switch common ground, the HIN signal needs a level shifter. (Optical isolation would be another technique beyond the scope of this discussion) As most gate driver ICs, I used a controlled current source to cross the possibly varying voltage differential. As noted in the schematic, on state current is designed to about 2 mA, off-state is zero. The current level is intended for a low bus voltage only and would cause too high power dissipation in a high voltage driver.

The control current is converted to a voltage by a load resistor in the high side part. A diode is limiting the control voltage not to go below the negative supply of the high side driver.

3. The bootstrap circuit is identically to the standard circuit used with most driver ICs, also discussed in a previously suggested publication. It requires the low side switch to be activated first to load the boostrap capacitors and doesn't allow zero duty cycle for low side switch.

4. The driver must basically supply the dynamic gate current, according to the intended switching characteristics. Additionally, it may be desirable to make it guarantee defined on/off state, particularly prevent from MOSFET desaturation, but this simple circuit doesn't.

I've used a similar high side driver circuit in a electronics lab experiment, thus I know it's basically working. For real (production) designs, I prefer driver ICs or a combination of ICs and discrete power transistors for high current drivers dedicated to above 100 amps power stages.

As I don't intend to write another power electronics text book (there are good ones), I'll finish this short explanation now.

 

[Mr.Cool]

schematic of and gate

the only problem with discrete ICs for high power application is that SOME of them have long propegation delay. this will translate into a need for long deadtime which results in low frequency harmonics and thus high THD at the output of your inverter.

your gate driver circuit must also be knowledgable of the different types of fault that can occur. the gate drive must immediately shut down in presence of fault and notify the system so that the system (DSP?) can then shut-down all gate drives. how long does this process take? your power switch must be rated to survive the fault current for the duration of this shut-down process.

Mr.Cool

 

[FvM]

discrete high side driver

Generally, the discussion wasn't based on a clear specification. The requirements may be very different of course. The features you're mentioning now (e.g. some kind of fault handling) are clearly going beyond this thread's scope. Obviously, they are essential for some applications.

For more basic applications, I see e.g. IRF level shifting drivers as a reference. They don't have any dedicated fault monitoring, except for a low-voltage shutdown. As I mentioned, they are superior to various homebrewed driver designs by this simple feature.

Of course, you can design a high performance gate driver with features from discrete devices and standard IC, something like the Eupec/Infineon modules, intended to drive IGBT converters up to MW capacity. But that's a different discussion.

 

[Mr.Cool]

or gate schematic

yep.

 

[santom]

discrete high side drive

@ FvM,
Thanks for your detailed explanation about the circuit.I have got a rough picture about the circuit which is better than how I was in the past.

I am trying to implement for a full bridge and also two separate outputs from two comparators both positive and negative separately.
So what all I have to add to that schematic to apply for full bridge circuit.

Thanks in advance

Santom

Added after 12 minutes:

@FvM. Why do we need to have Common Collector Output stage when we are trying to realise an inverter 4069 by means of discrete components?

Can u explain that to me please.?

 

[FvM]

gates discrete faults

Common collector stage is actually a non-inverting driver in contrast to 4069, but it's preferred as a gate driver usually. You have to add an inverting stage, if required for the intended signal polarity.