direct digital synthesizer implementation on FPGA

[kami70b]

i wanna know how the phase accumulator works in DDS. if i give a discrete frequency input to DDS how will it generate frequency corresponding to input. i wanna use it in phase lock loop.

 

[FvM]

I'm under the impression, that the DDS IP documentations have good explanations of it's basic operation, it's at least the case for the Altera DDS core.

It's very easy anyway. Simply consider an accumulator of any length, e.g. 32 bit. The frequency value is added each clock cycle, the accumulator is representing the signal phase. An overflow means starting a new signal period. N most significant accumulator bits are output to a sine table to give the output signal.