Sasha_Mishutina
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Hello! I make digital phase detector for wander measuring. I have clock=2 MHz(with wander) and reference clock: clk=200 MHz without any wander or jitter. Here is circuit, which I try to write in Verilog:
And here is diagram of circuit:
Here is the Verilog code:
Questions:
Is it good circuit for wander measurement?
Is there any mistakes in Verilog code?
Is this code good for really wander measuring device?
And here is diagram of circuit:
Here is the Verilog code:
Code:
module dpd31
(
input wire clk, reset, //reference clk=200MHz, reset
input wire clockW, //clock with wander ~2 MHz
output reg done_tick,
output wire edg, //edg=1 when positive edge clockW
output wire [21:0] x, //result
output reg [21:0] counter
);
localparam [2:0]
zero0 =3'b000,
count0 =3'b001,
done0 =3'b010,
zero =3'b011, //zero state: edgecounter=0
count =3'b100, //count state: counts edges from 1 to N
done =3'b101; //if edgecounter=N x_reg=counter.
localparam N=5; //counts for 5 edges of clockW
//***to avoid metastability:
wire sync_clock;
reg sync_ff1, sync_ff2;
always@(posedge clk)
sync_ff1<=clockW;
always@(posedge clk)
sync_ff2<=sync_ff1;
assign sync_clock=sync_ff2;
reg [2:0] state_reg, state_next;
reg [15:0] edgecounter_reg, edgecounter_next;
reg [21:0] x0_reg, x0_next, x_reg, x_next;
reg delay_reg;
always @(posedge clk, posedge reset)
if(reset)
begin
state_reg<=zero0;
edgecounter_reg<=0;
delay_reg<=0;
x_reg<=0;
x0_reg<=0;
end
else
begin
state_reg<=state_next;
edgecounter_reg<=edgecounter_next;
delay_reg<=sync_clock;
x_reg<=x_next;
x0_reg<=x0_next;
end
//rising-edge tick
assign edg=~delay_reg&sync_clock;
//
always @(posedge clk)
if(counter==(100*N)-1)
counter<=16'b0;
else
counter<=counter+16'b00000001;
//**********************************************
//FSM
always @*
begin
state_next=state_reg;
done_tick=1'b0;
edgecounter_next=edgecounter_reg;
x_next=x_reg;
x0_next=x0_reg;
case (state_reg)
zero0:
begin
edgecounter_next=0;
state_next=count0;
end
count0:
begin
if(edg)
if(edgecounter_reg==N-1)
state_next=done0;
else
edgecounter_next=edgecounter_reg+1;
end
done0:
begin
done_tick=1'b1;
state_next=zero;
x0_next=counter;
end
zero:
begin
edgecounter_next=0;
state_next=count;
end
count:
begin
if(edg)
if(edgecounter_reg==N-1)
state_next=done;
else
edgecounter_next=edgecounter_reg+1;
end
done:
begin
done_tick=1'b1;
state_next=zero;
x_next=counter-x0_reg;
end
default: state_next=zero;
endcase
end
assign x=x_reg;
endmodule
Questions:
Is it good circuit for wander measurement?
Is there any mistakes in Verilog code?
Is this code good for really wander measuring device?