difficalty with full scan testing: what is scan mode and what is capture mode

[fatma123]

hello
can somebody explains to me in brief full scan testing because I have difficulty to understand this type of testing. what happens during scan mode and what happens during capture mode???

thanks in advance

 

[rca]

there are two phases, the shift phase, all flop are chain together and the tester define their values, then the capture phase occurs, the flop are connected as functionnal mode, and one (or more) clock pulse are generated to capture the combinational value between two flops, then the shift phase occurs again to read the capture value and provide the new flop state for the next capture phase.

full scan testing means (I beleived), all flops (as possible) are included in the scan chains, you could exclude some part of the design to do a partial scan, but, how you could covers this part during production test?, it is a trade off between coverage and test time and patterns size.

 

[shobhit]

How do we switch b/w scan and capture modes on the fly, and how does a timing tool check for STA in capture modes?
I mean that it is easy to take care functional and scan shift modes, by putting case analysis on scan enable and then checking STA, but how do we put the chip in scan capture mode immediately after scan shift and that too on the fly and at the same time check STA?

 

[rca]

you define to the DFT tool, a capture/shift signal, this signal is RTL coded and directly controlled by a pad when the chip is in scan mode.
so this signal is also check by STA.
The dft tool connects this signals to all SE pin of flop and the output dft mux which select the scan chain out or the functional out on scan chain output pad.
that's fine?

 

[shobhit]

I think you did't get what i was asking .......

STA has to be run in different modes of the chip
1) Functional Mode { condition Scan Enable = 0 & functional clocks are used}
2) Scan Shift mode { condition Scan Enable = 1 & shift clock (a slow clock) is used}
3) Transition fault testing mode {??????????????????????}

It is this condition that I was asking

I know that transition fault testing is done after the data has been shifted and then launch and capture is done at functional frequency.

as far as I know the procedure is
scan shift data -----> launch and capture data at func freq. -----> scan shift data --------> launch and capture at func. freq...... and keep on repeating.

One understands the way this will be achieved functionally ie: by toggelling the SE and alternatively passing slow clock and then functional clock..

BUT HOW WILL A DESIGNER MIMIC SUCH A SITUATION TO A STA TOOL ?????????


i hope u get it now

 

[rca]

Sorry shobhit, but in your first question you never mention the transition fault model. Good luck!

 

[honey13]

Hi shobhit,

What are the tools you are using for scan insertion.Can you provide some information of On-chip-controller block like how u r providing the high frequency clock, tool inserted or manually inserted OCC...

 

[zic]

Hi Shobhit,
In fact, there are several mode for STA check with different SDC:
1) function mode: functional sdc
2) DC shift: low speed shift, SE=1;
3) DC capture:low speed capture, SE=0;
4) AC shift:low speed shift, SE=1;
5) AC capture:high speed capture, function clock, SE=0

Hope it can help you!

 

[owen_li]

Hi Zic.

As you said, SE will be kept as an constant in all the timing mode.
Then How can tool constain the timing of SE ?
I think we should gurarantee it should be only kept 0 in capture cycle.
How can tool make SE work well and check it is ok enough when signoff ?

Thanks!

 

[morris_mano]

Considering shift cycle and capture cycle for ATPG, immediately after shift clock pulse, the constraint would be that the data path time to capture flop should be less than the time difference between shift clock edge and subsequent capture clock edge.

After shift clock pulse, the data will have already traveled from Q pin of flop through combination path to D pin of capture flop without waiting for SE signal to go low. SE pin can change anywhere between shift pulse and functional capture pulse. From my understanding, only constraint for SE signal will be to not change close to functional capture pulse.

 

[owen_li]

Thanks for your response, morris_mano.
You are right.
But, even though the timing is very loose for scan enable to meet, we also code timing rule to check it.
And in ASST, the scan enable timing is very critical, coz the frequency of the function clock is very high.
If we don't consider the timing of SE, it will damage the test of the chip.
Am I right ? thanks!

 

[morris_mano]

And in ASST, the scan enable timing is very critical, coz the frequency of the function clock is very high.
If we don't consider the timing of SE, it will damage the test of the chip.
Am I right ? thanks!

Yes, you are right. For high frequency fuctional clock, I can see SE causing issue. SE is routed to all scannable flipflops so , if you don't build a balance tree for it, some flops may see positive skewed SE, which may violate timing on the capturing flops.

But, on ATE, you will have control over when to pulse shift clock, function clock and toggle SE. So, you could still test the chip correctly but at lower frequency.

From my understanding, scannable flops have built in timing constraint(setup & hold) when SE is allowed to change with respect to CLK pin. When you do timing analysis, instead of putting SE to constant by set_case_analysis, what if you allow the timing analysis without having SE constant. I believe, the tool will analyze the path from launching flop to capturing flop with respect to SE as well and report violation if there is any.

 

[owen_li]

When you do timing analysis, instead of putting SE to constant by set_case_analysis, what if you allow the timing analysis without having SE constant. I believe, the tool will analyze the path from launching flop to capturing flop with respect to SE as well and report violation if there is any.

I think that is right way too.
But another issue ocuurs.
If you don't set SE constant on scan shift mode, the scan_enable is just checked under the scan clock group.
So the timing of SE is not well constrained under ASST, coz it should shift swiftly witin the capture cycle.

If you don't set SE constant on scan capture mode, the scan_enable will be checked under functional clock group.
However, the shift path timing will also be included in this mode now, coz scan enable has no case analysis set.
Then, the timing report will be messed up with both scan shift timing paths and scan capture timing paths coming in.

So how do you handle this case in your previous projects ?
How to write the SDCs to fix this issue ?

Thanks!