different clock domain

[uckingcu]

creat_generated_clock

Hi,
I have two clock domains, clock in one domain is shifted by 90 degrees when compared to other clock. How to handle the data between these domains?

 

[dft_guy]

Depends upon how many signals you need to safely get across the domain boundary, but in general, regardless of the amount of phase offset, you need to synchronize them on the receiving side.

For a few signals, that involves a two flop synchronizer to weed out the metastability.

For large amounts of signals, you may want to set up a proper asynch boundary with req/ack communication.

John
DFT Digest

 

[chiguoquan]

Three ways:
1) synchronizer .Only for one bit signal.
2) req/ack communication.
3) asynchronous FIFO.

 

[moorehuang]

using FIFO mostly

 

[rameshsuthapalli]

Hi all,

there is one more solution for that.if these clocks are genrated from the same point of source.you can declare a derived clock with derivation factor as 1 and phase difrence of 90degrees so tool will take care of the synchronization effects.

regards,
ramesh.s

 

[uckingcu]

Ramesh..can you explain more clearly how should i use derivation factoe you described?

 

[sumit_techkgp]

Use synchronizer at the clock domain crossing
Sumit

 

[quan228228]

Ramesh..can you explain more clearly how should i use derivation factoe you described?

In synthsis process, you can use "creat_generated_clock" command to implement this situation.

i amply agree with solution of "chiguoquan".

/David

 

[sumit_techkgp]

Hello,
Please synchronize the clock domain. It means use a two stage synchroniser on the input clock. During synthesis use this path as false paths.
Sumit