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There are two opamps(cmos):the first stage are the same(nmos input),but the second stage is different,one is nmos and the other is pmos, what is the difference?
First of all, can you be more specific? The first stage is using nmos input, that ok,but the second stage with nmos and pmos input? how do you design your second stage?? Is it the same arhitecture with the first one or it's differ?? Let us know...
Your question is a little bit covered. It is not open.
By saying nmos input stage, I quess, you have wanted to mean nmos differantial pair. Otherwise, input sage must have pmos and nmos transistors togather.
For output stage, It is impossible to answer your question exactly. You have to explain the output stages more. But I can say GENERALLY that if pmos used anywhere the current flows from possitive rail to any point. If nmos is used in any circuit current sinks from any point to negative rail.
yes, gain is one aspect of the diffence, but this diffence is not the key. The most important diffence is the match problem between the 1st and 2rd stage, but who can analyse this in detail?
"The most important diffence is the match problem between the 1st and 2rd stage, but who can analyse this in detail?"
I think it's depends on what is the output voltage from 1st stage to be inserted to 2nd stage! But must make sure all the transistors in the 2nd stage are saturated!
Another thing is left one provide high pull-up output current with limited pull-down current. The right one provide limited pull-up output current and high pull-down current. So you must consider your load.
Another thing is left one provide high pull-up output current with limited pull-down current. The right one provide limited pull-up output current and high pull-down current. So you must consider your load.
If load of right circuit is resistor connected to ground there can be not enough output current because that is limited by current source connected between Vcc and output. For left circuit the same situation will be when load resistor connected to Vcc.
I think the two ouput stages are all class-A. Because for current consumption limit issue, the output stage bias current is low. So
the sourcing or sinking capability is limit by constant current source.
I think the matching does nothing between 1st stages and 2nd stage, so there is no matching issue here (of course, the diff pair along need to be match!)
I also agree with that it highly depends on the loads. The two circuit provide different current driving capability to sink or source current.
Probably one of the difference is the speed. Since this is miller compensated two-stage op, the second pole will be determined by the second stage's gm, so having NMOS as output transistor will be faster than the PMOS one (or equivalently, having large Phase Margin than PMOS).
I also agree with that it highly depends on the loads. The two circuit provide different current driving capability to sink or source current.
Probably one of the difference is the speed. Since this is miller compensated two-stage op, the second pole will be determined by the second stage's gm, so having NMOS as output transistor will be faster than the PMOS one (or equivalently, having large Phase Margin than PMOS).
Terryssw,
I aggre with the current sink and source capability as a difference between two circuits. The left circuit can source current while the right can sink current.
I aggre with the explainations on second pole.
But I could not understand the words on Phase Margin. Because this is an analog circuit but not any Digital gate circuit !!!
When design a opamp you also need to consider the DC voltage level balance. In order to get the same voltage swing on output as that on input, the DC voltage level should be the same.
Therefore the second stage of opamp usually has the functionality of DC voltage level shifting. This means if the input stage uses NMOS then you need to use PMOS to do the level shifting, if input is PMOS then NMOS will be used.
Maybe you can search the internet for the details of this issue.
i think load is not a critical requirement in this case.
bcoz o/p pole = gm/CL..since NMOS has high gm value,second pole frequency is higher if it is NMOS.
correspondingly phase margin will change.
I think one difference might be the systematic offset caused by different current densities. The left one can reduce offset by making Vgst(MP5)=Vgst(MP3/MP4)
i.e 2Id(MP5)/(W/L)5=2Id(MP3)/(W/L)3
The right one can not. I think Gray&Meyer's book describes that.
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