tariq786
Advanced Member level 2
Hi guys,
sorry for may be asking a simple question.
We know that for "Registers" in a design, the timing difference between RTL and Gate-level (timing) simulation cannot exceed the clock period minus the setup time because else there would be a setup time violation.
Now can we say the same thing about combinational logic wires? or is the delay between RTL and Gate-level (timing) simulation for combinational logic arbitrary?
Please educate me.
Thanks in advance.
sorry for may be asking a simple question.
We know that for "Registers" in a design, the timing difference between RTL and Gate-level (timing) simulation cannot exceed the clock period minus the setup time because else there would be a setup time violation.
Now can we say the same thing about combinational logic wires? or is the delay between RTL and Gate-level (timing) simulation for combinational logic arbitrary?
Please educate me.
Thanks in advance.