ikru26
Banned
1) A single ALM has max of 8 input
ie 2 LUTs or ALUTs
either it can have same size or different size.
eventhough the max input is 8 we are using only 7 inputs in all the cases .
2) can anyone tell me some differences between @ltera ALM and what is the equivalent in Xilinx. ( ALM_ Adaptive logic Module ).
3) Difference between
1) LUTs in Xilinx and @ltera
2) DLL's and PLL's
3) Architecture wise between Stratix ii and Virtex 4
3) what are the major differences in @ltera FPGA mainly Stratix II with Xilinx Virtex -4 pro
ie 2 LUTs or ALUTs
either it can have same size or different size.
eventhough the max input is 8 we are using only 7 inputs in all the cases .
2) can anyone tell me some differences between @ltera ALM and what is the equivalent in Xilinx. ( ALM_ Adaptive logic Module ).
3) Difference between
1) LUTs in Xilinx and @ltera
2) DLL's and PLL's
3) Architecture wise between Stratix ii and Virtex 4
3) what are the major differences in @ltera FPGA mainly Stratix II with Xilinx Virtex -4 pro