difference between DCM clock and Clock divider Block

[mudasir]

cycloneii_clkctrl

hi

we can generate different clock frequencies from the master clock by writing simple clock divider modules

Also we can generate different clock frequencies from the master clock by using
digital clock managers (DCMs).

Whats the difference between the two?
What is the advantage of using DCM?
Kindly any one plz explain the difference between the two

 

[gck]

clock divider

In case of FPGA, clock is rooted on special route called as clock tree through clock buffers. This is specialy meant for avoiding clock skew and related problems.

When you use clock divider module for generating other derivatives of the clock. then your master clock gets routed on ordinary routs.

There is no provision which will bring the clock on clock tree.
Again the DCM is specially meant for handling such clock related problem. You need not worry about .

 

[j_andr]

dcm clock divider

Whats the difference between the two

/.../then your master clock gets routed on ordinary routs

this is not true, at least not always true;
I've made a small example:

module clock_tree
(
   input             clk_in,
   output reg [16:0] sum
);
reg [ 3:0] clk_div = 0;
reg [15:0] cntA, cntB;

always @(posedge clk_in)
   clk_div <= clk_div + 1; //  clock divider
   
wire clk = clk_div[3];  // 'devided' clock;

always @(posedge clk)    
  begin
    cntA <= cntA + 1;
    cntB <= cntB + 2;
    sum  <= cntA + cntB;
  end
endmodule

and generated netlist by quartus:

module 	clock_tree (
	clk_in,
	sum);
input 	clk_in;
output 	[16:0] sum;
wire \cntB[4] ;
/.../
cycloneii_clkctrl \clk_in~clkctrl_I (  // <== clock control module
	.inclk({clk_in}),                   // <== input
	.outclk(\clk_in~clkctrl ));         // <== global clock
defparam \clk_in~clkctrl_I .clock_type = "Global Clock";
defparam \clk_in~clkctrl_I .ena_register_mode = "falling edge";
/.../
cycloneii_clkctrl \clk_div[3]~clkctrl_I (
	.inclk({\clk_div[3] }),
	.outclk(\clk_div[3]~clkctrl ));
defparam \clk_div[3]~clkctrl_I .clock_type = "Global Clock";
defparam \clk_div[3]~clkctrl_I .ena_register_mode = "falling edge";

cycloneii_lcell_ff \cntB[1]~I (
	.clk(\clk_div[3]~clkctrl ),
	.datain(\cntB[1]~85 ),
	.regout(\cntB[1] ));

cycloneii_clkctrl is a cyclone clock buffer which drives
global clock net;

as you can see - the input clk_in goes to such buffer
and the buffer output \clk_in~clkctrl drives the clock
divider clk_div;
then last bit of the divider is also routed to a global clock
buffer and as a \clk_div[3]~clkctrl drives clock ports
of the remaining registers in the example;
I believe ise of xilinx has a similar strategy;

comming back to mudasir question;
with a counter you can only divide frequency, DCM can also
multiply it;
DCM can make any clock phase alignment, counter cannot;
if you need in your design a clock and a clk/4 - DCM can create
such clocks with 0 phase shift, a counter by definition
produces pretty large shift [delay on a counter itself and
then routing to a clock buffer];
sometimes such offset is not acceptable, sometimes one can
live with it;
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