madan_ratnakar
Newbie level 2
Hey!
I have a .bit file for Xilinx spartan 6 FPGA . I generated the SVF file for the .bit file that I have. I know that the .bit file is byte reversed ( each byte is bit reversed) but there are other differences as well in the file that I have, for example there are some hex values which are different while there are also some values extra in the end of the .bit file. I do not know/ understand these differences.
I am making my own Jtag programming utility using the Digilent HS1 cable and was sending the .bit file as the configuration file. There were some issues so I thought of taking a clue from the SVF file but now I am stuck here and do not know what to do!
Kindly help!
Regards
I have a .bit file for Xilinx spartan 6 FPGA . I generated the SVF file for the .bit file that I have. I know that the .bit file is byte reversed ( each byte is bit reversed) but there are other differences as well in the file that I have, for example there are some hex values which are different while there are also some values extra in the end of the .bit file. I do not know/ understand these differences.
I am making my own Jtag programming utility using the Digilent HS1 cable and was sending the .bit file as the configuration file. There were some issues so I thought of taking a clue from the SVF file but now I am stuck here and do not know what to do!
Kindly help!
Regards