mersault
Member level 2
Hello,
I'm working on a project in a spartan 3e with xilinx's ISE tool.
I made a half adder with schematic and this is the report
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-5
Number of Slices: 0 out of 4656 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 232 1%
I made the same half adder with verilog
module halfadder(a, b, sum, carry);
input a, b;
output sum, carry;
assign sum = a^b;
assign carry = a&b;
endmodule
and this is the report...
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-5
Number of Slices: 1 out of 4656 0%
Number of 4 input LUTs: 2 out of 9312 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 232 1%
why verilog programming uses a slice while the schematics doesn't?
there's a method to optimize area in verilog?
I hope that you could help me..
Greetings
pd: this is my first post.. so, hello to all the people of this forum
I'm working on a project in a spartan 3e with xilinx's ISE tool.
I made a half adder with schematic and this is the report
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-5
Number of Slices: 0 out of 4656 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 232 1%
I made the same half adder with verilog
module halfadder(a, b, sum, carry);
input a, b;
output sum, carry;
assign sum = a^b;
assign carry = a&b;
endmodule
and this is the report...
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-5
Number of Slices: 1 out of 4656 0%
Number of 4 input LUTs: 2 out of 9312 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 232 1%
why verilog programming uses a slice while the schematics doesn't?
there's a method to optimize area in verilog?
I hope that you could help me..
Greetings
pd: this is my first post.. so, hello to all the people of this forum