DFT query about netlist that has flops with clock enable pin

[anssprasad]

Hi,

If in my netlist I have flops with clock enable pin, will the netlist be considere as one which has gated clocks.

Thanks
Prasad

 

[avimit]

Re: DFT query

No, the netlist will not be considered as the one which has 'gated clocks' because the enable pin controls the D input inside the FF, and not the clock.
kr,
Avi

 

[anssprasad]

Re: DFT query

No, the netlist will not be considered as the one which has 'gated clocks' because the enable pin controls the D input inside the FF, and not the clock.
kr,
Avi

Hi,

But I am using a lowpower library which might actually gate the clock input internally and not the data input using the enable.

Thanks
Prasad.

 

[avimit]

Re: DFT query

Well, in that case you will need to see the library spec then. I will still say that the lib vendor will not play with the clock, but to be sure, you will have to look into the lib spec. You can also have a look into the .lib file and see what are the pin functions there. Or looking at timing arcs in the .lib file may give you a clue whats going on insed the cell.
kr,
Avi

 

[anssprasad]

Re: DFT query

I have finally found what the issue was but could not trace to its origin. The pin connections of the flops with enable in my design were interchaged as follows:
CP --> E
E -- > D
D --> CP

When I realigned them in the netlist manually I could get the lec pass on the pre and post scan netlists.

 

[Amruth]

Re: DFT query

we cant conform with that our design has gated clock. every flop has clock enable pin . gated clock is use to enable particular logic ( group of flip flops)