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salamander said:Hi,
simply an @always posedge clock block where you count an reg from 0 to 2 an then toggle clock_slow (clock_slow=~clock_slow).
Now you can use clock_slow as your 8Mhz Clock...
// Divide by 3 module
//
module divide(
CLK,
DIV3
);
input CLK;
output DIV3;
reg cnt_a, cnt_b;
always @ (posedge CLK)
begin
cnt_a <= ~cnt_a & ~cnt_b;
cnt_b <= cnt_a;
end
assign DIV3 = cnt_b;
endmodule
silencer3 said:there is a pdf fine from st micro-electronics. That is an excellent note on how to divide clock with 50% duty cycle and you can divide with odd numbers also. search net for pdf file st clock divider. this is patented one.