devices for outputting double the clock frequency?

[janw]

coolrunner ii jitter

Hi, I'd like to have your suggestions for what CPLD/FPGA part to use for doubling a 5-10 MHz input clock, then outputting this on some pins.

The duty cycle of the "clk2x" output clock would need to be 50% and jitter should be not much worse than the input jitter. In vs out phase difference does not matter. There is some extra counter and event timer stuff going on also, simple, but still I'd rather like to avoid a separate PLL chip if possible.

The problem seems really easy...

But I already looked a bit and found Xilinx CoolRunner-II with the Clock Doubler marketing feature, then noticed this only means it has dual-edge flipflops.

There are also Spartan-3 with their DCMs, but while I didn't find any real jitter figures, other postings say that for 5-10MHz reference I need to use DFS mode and then the jitter can be "quite bad". And FPGAs are $$$ compared to CPLD.

Finally I found the Lattice MachXO, it is supposed to contain some sort of a PLL.

Does anyone know a MachXO micromodule?

Or maybe you know some better solution?

Some other CPLD that trivially can double an input clock and output this clk2x?

Thanks!

 

[pev]

double clock frequency

Can I suggest using an analogue component (from mini circuits or equivalent).

If jitter is a problem. FPGA/CPLD will probably introduce a lot more jitter as they are effectively a digital component. I believe DCM and PLL have to add jitter for them to even work. But you may still be able to use them depending on how clean you need the signal.

If your only using the device to multiply the clock why don't you get something specifically designed for that purpose?