Designing an ring oscillator + buffer question

[Justin Wenger]

I was designing a 5-stage CMOS ring oscillator + 2 stage buffer on Pspice,

I want to make the output frequency to 1GHz, and I chose to make every Transistor Legnth L = 0.2um

So I decided to change the W of every transistors to get the 1GHz frequency, and made the ring oscillator's transistor width Wn = 7um, Wp = 22um(Since Wp:Wn = 3:1)

But when I tried to make 1GHz frequency, I had to make the W of stage buffer transistor sooo big (more than 600um) and I realized it was too big for layout.

Is there a way to get 1GHz without making the width of stage buffer too big?

 

[frankrose]

why do you have to drive 1pF? decrease your load cap.
and increase supply voltage if your devices can tolerate higher VDD

 

[dick_freebird]

What do you want for output swing and Zload? A RF chain would not want rail-rail except maybe for LO drive of a.mixer quad. You could assert a lighter load for on chip only. You could declare a lesser signal swing and demand the PLL guy bring his own input buffer. Like that.