Designing a CMOS op-amp

[prestonee]

Its best to simulate to see your openloop if you are verifying.
I expect you took -gm*ro and converted it to -2Va/Vov or -2/(lambda*vov). so the question is do you have rds, Va, or lambda. you should have something like this.
you should be able to find one of these parameters in your spice deck.
-Pb

 

[Junus2012]

Then you have to extract it by yourself, I have attached you a book, go to page 79, it gives you a method how to extract it by simualtion

 

[prestonee]

How did this project go?

 

[InspectorGadget]

The project is going well. I've managed to meet all the specs that were set out so far.

My one problem with the design is that I'm seeing a systematic offset voltage on the output when performing my transient analysis (well it's always there, just obvious with transient).
I've sized my transistors according to the formula S6/S4 = 2(S7/S5) where S6 is the lower NMOS of the output stage, S4 is NMOS of diff pair, S7 is PMOS of output stage and S5 is PMOS of differential stage current mirror. I thought that following this sizing that the offset voltage is supposed to be zero?