Designing a 2's Complement Multiplier

[Digit0001]

Hi

Can someone give me some advice on designing a 2's complement multiplier
I started by creating a state graph and this is what i have:

**broken link removed**

One problem i am stuck is what exactly should be in S7 when M = '1'? I had in mind four cases that should be cover by using case statements:

Multiplicand is positive, multiplier is positive
Multiplicand is negative, multiplier is positive
Multiplicand is positive, multiplier is negative
Multiplier is negative, multiplicand is negative

I would appreciate if someone gave me some other suggestions?

P.S

 

[TrickyDicky]

With twos compliment, there is no need to worry about whether values are positive or negative. All you need to do is sign extend both inputs. You either need to instantiate an onboard multiplier or N adders, where N is the number of bits at input.

lets take an example, -3 x 5 (1101 x 0101)

                 1 1 0 1
x                0 1 0 1
------------------------
         1 1 1 1 0 1 0 0
+        1 1 1 1 1 1 0 1
------------------------
         1 1 1 1 0 0 0 1   (-15)

Bits higher than bit 7 are ignored, because the output result is 8 bits. (two 4 bits inputs gives an 8 bit result).

 

[qieda]

Hi TrickyDicky,

how would the example look like for -3 x -5 (1101 x 1011)?
The final result should be 1111 = 15

Thanks.

 

[Digit0001]

How exactly would i check the condition 10110000 x 11100000?

I tried the following code in VHDL, but it does not work? any suggestions for solutions?

Mcand is the Multiplicand
Mplier is the Multiplier

snippet from code:

signal M_final,C_final : std_logic_vector(7 downto 0);

elsif ((Mcand(7) & Mplier(7)) = "11") then
			C <= (not Mcand) + '1';
			M <= (not Mplier) + '1';

---------- Post added at 03:40 ---------- Previous post was at 02:36 ----------

nvm i found out how to do it

 

[qieda]

Hi Digit0001,

I'm not so familiar with VHDL but in verilog I can use signed singals to do twos complement multiplication without checking the sign bit.

see example

module tb  ();

   reg signed [7:0] mcand;
   reg signed [7:0] mplier;

   wire signed [15:0] result;


   initial
     begin
        // -80 x -32
	mcand  = 8'b10110000;
        mplier = 8'b11100000;

        // 80 x -32
	#100000
	mcand  = 8'b01010000;
        mplier = 8'b11100000;

        // -80 x 32
	#100000
	mcand  = 8'b10110000;
        mplier = 8'b00100000;

        // 80 x 32
	#100000
        mcand  = 8'b01010000;
        mplier = 8'b00100000;
        
	#100000
        mcand  = 8'b00000000;
        mplier = 8'b00000000;
           
     end

   assign result = mcand * mplier;
   

endmodule

 

[TrickyDicky]

The result isnt 1111, it is 00001111 (remember, two 4 bit inputs give a 8 bit result):

All inputs are sign extended for the purpose of multiplying:

  1 1 1 1 1 1 0 1
x 1 1 1 1 1 0 1 1  
---------------------
  1 1 1 1 1 1 0 1   2^0
+ 1 1 1 1 1 0 1 0   2^1
+ 0 0 0 0 0 0 0 0   no 2^2 component
+ 1 1 1 0 1 0 0 0
+ 1 1 0 1 0 0 0 0 
+ 1 0 1 0 0 0 0 0
+ 0 1 0 0 0 0 0 0
+ 1 0 0 0 0 0 0 0
---------------------
  0 0 0 0 1 1 1 1     = 15