Design on FPGA power and speed??

[lmtg]

How can one reduce power of one's design that was written by vhdl and downloaded on fpga?

Is there a relation between the design areaand consumed power?

Any good sitesyou could reference me to?

Thanks : )

 

[farhada]

There are many things you can do to lower your power, but all of these must be done in design and not after it is loaded into the chip.

One is to lower your clock, use clock gating and dissable the clock when parts of the design are not needed.

Other is to make sure all your IOs are dissabled or high-z when it is not necessary to actively drive those signals.

Just to name a few, help it helps.

Best regards,
/Farhad