design of counters..pl help!

[cutesue]

This is a design question. Please design a counter that counts the number of times the
number “5†appears in an 4-bit input stream. The I/O are as follows:

NumberIn : 4-bits wide (input)
Start: Reset counter and overflow flag to zero while start is high (input)
Count: 8-bit unsigned count (of the number of “5â€s that have occurred since start went
low (output)
Overflow: Goes high if count overflows (count is unsigned, so you only need to monitor
the adder carry out) and stays high until start is re-asserted.

 

[Aritra Mukherjee]

First of all covert the input in parallel if its in series then using logic gates design a combination that gives one only when 5 is pressed and this output goes to an adder which u can monitor easily......

 

[umerhuzaifa]

I agree with Aritra.
Just to add.
Be mindful of the rate at which the input data stream flows in.
If the data stays for say "Ts", your combinational circuit delay should not be more than "Ts" otherwise you would miss a few data sets.

Regards,