javierh.santiago
Junior Member level 2
Hello,
I am doing synthesis for different RTL components (Combinational Circuits) with Design Compiler from Synopsys, and I would like to optimize for maximum performance in terms of power, area, and delay independently i.e. one netlist for each optimization (total 3 circuits for each component). I am using following constraints for delay and area, but I don't not how to do it for power yet. Do you know what are those constrains?
AREA:
set_max_area 0.0
DELAY:
set_max_delay 0 -from [all_inputs] -to [all_outputs]
POWER:
any advise???
thanks
I am doing synthesis for different RTL components (Combinational Circuits) with Design Compiler from Synopsys, and I would like to optimize for maximum performance in terms of power, area, and delay independently i.e. one netlist for each optimization (total 3 circuits for each component). I am using following constraints for delay and area, but I don't not how to do it for power yet. Do you know what are those constrains?
AREA:
set_max_area 0.0
DELAY:
set_max_delay 0 -from [all_inputs] -to [all_outputs]
POWER:
any advise???
thanks