juliog
Newbie level 6
Hello guys,
Is it possible to tell design compiler that is it only allowed to change gate strengths during a compilation? E.g., changing AN2S gate por AN2T gate. Obviously, the input would be a circuit (netlist) already mapped into a technological library.
In other words, after a first compilation and mapping, I set new constraints and run additional compilations. I don't want these latter compilations to alter the structure of the circuit, but only to change gate strengths in order to try to fulfill new constraints.
Any way to achieve this behavior? I tried different options, but it wasn't possible.
Thanks!
Is it possible to tell design compiler that is it only allowed to change gate strengths during a compilation? E.g., changing AN2S gate por AN2T gate. Obviously, the input would be a circuit (netlist) already mapped into a technological library.
In other words, after a first compilation and mapping, I set new constraints and run additional compilations. I don't want these latter compilations to alter the structure of the circuit, but only to change gate strengths in order to try to fulfill new constraints.
Any way to achieve this behavior? I tried different options, but it wasn't possible.
Thanks!
