FreshmanNewbie
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I am having this MAX9278 deserializer IC.
The input to the pins +IN and -IN is a twisted pair input and therefore, it is a differential signal. I have configured the CX/TP pin to low since it is a twisted pair input to IN+ and IN-. I hope this is correct. (Referring table 10).
My question is,
I have interfaced the above deserializer with a 3.1 inch TFT which has a resolution of 800 x 480 pixels. IN+ and IN- twisted pair input and 4 LVDS Channel output and a LVDS Clock output to the TFT.
My frames per second requirement is 60 and blanking is 20%.
In that case, according to this formula from Maxim, my PCLK,
My Calculation:
Question 1: Whether the calculation of my PCLK is correct? If it is correct, will all the LVDS Data output channels also be going to the TFT at 27.6MHz?
Question 2: From where does the 27.6MHz is generated. There is no crystal which is connected to the deserializer. However, there are 2 blocks as marked below.
So, does the blocks generate the clock or does it take the input IN+ and IN- and perform clock data recovery (there is no mention of clock data recovery in the datasheet) from the IN- and IN+ data and provide the same to the LVDS outputs? Which means that I need to send my signals IN+ and IN- at 27.6MHz? Am I correct?
The input to the pins +IN and -IN is a twisted pair input and therefore, it is a differential signal. I have configured the CX/TP pin to low since it is a twisted pair input to IN+ and IN-. I hope this is correct. (Referring table 10).
My question is,
I have interfaced the above deserializer with a 3.1 inch TFT which has a resolution of 800 x 480 pixels. IN+ and IN- twisted pair input and 4 LVDS Channel output and a LVDS Clock output to the TFT.
My frames per second requirement is 60 and blanking is 20%.
In that case, according to this formula from Maxim, my PCLK,
My Calculation:
Question 1: Whether the calculation of my PCLK is correct? If it is correct, will all the LVDS Data output channels also be going to the TFT at 27.6MHz?
Question 2: From where does the 27.6MHz is generated. There is no crystal which is connected to the deserializer. However, there are 2 blocks as marked below.
So, does the blocks generate the clock or does it take the input IN+ and IN- and perform clock data recovery (there is no mention of clock data recovery in the datasheet) from the IN- and IN+ data and provide the same to the LVDS outputs? Which means that I need to send my signals IN+ and IN- at 27.6MHz? Am I correct?