semiconductor
Full Member level 4
My lecturer in Digital communication subject has assigned us a project:
I'm take deep steps into this project but I only understand in terms of theory. I don't know how to design circuitry of this Demultoplexer (esp. frame and multifram alignment in synchronization).
In the 24-channel Format, each frame contains 24 slots and 1 bit for frame alignment. Every 6 slots, in the 8-bit code, 7 bits for information coding and 1 bit for signaling --> That's all I know about this system
Can some one tell me more and raise some ideas for me to design the circuitry of the DEMUX!
If you have done the same project as mine or you have got the circuitry already, can you share it with me?
Thank you before hand!
design Digital Logic circuit to implement the following task: demultiplex the PCM bit sequence in T-1 (24-channel) system (and also synchronize).
I'm take deep steps into this project but I only understand in terms of theory. I don't know how to design circuitry of this Demultoplexer (esp. frame and multifram alignment in synchronization).
In the 24-channel Format, each frame contains 24 slots and 1 bit for frame alignment. Every 6 slots, in the 8-bit code, 7 bits for information coding and 1 bit for signaling --> That's all I know about this system
Can some one tell me more and raise some ideas for me to design the circuitry of the DEMUX!
If you have done the same project as mine or you have got the circuitry already, can you share it with me?
Thank you before hand!