delay loop insertion inside cpld (help!!!)

[tsehonkit]

Do anyone know how to insert a delay loop between two nets inside Xilinx 95108 CPLD?

 

[ASIC]

You want the delay to be a multiple of the clock period right? You can do that using a string of flip-flop.

If you want a small delay between two nets, i.e. 10 ns or something like that. It is going to be tough. You can try setting some constraints before place and route, or you route the signal to an output pin, place a small capacitor on the pin to ground (some pF), and route it back in again through an input pin.



ASIC

 

[tsehonkit]

I am doing a asyn circuit in a cpld. There is no clock signal. I tried using delay constrain, it did not work. Finally I found out a nand latch can delay around several ns depanding on the chip speed. As it contain a feedback loop, so it will not logic optimized by the tool.

 

[dll_embed]

It's not a recommended way to rely the correctness of your circuit on delay in cpld/fpga. The redundent path will be optimized out. And if it is not optimized out, the delay will keep change from P&R to P&R. Your circuit is not predictable. The cpld/fpga is not designed for this kind of usage.

If you really want to use delay in your design, try to route the net out of cpld and then link it back through pad. In this way the delay is more predictable(pad to pad delay).

regards

 

[Hero]

Hi,

Alaways use synchronous logic. If you need some delay between signals use external fast clock e.g 20MHz for fast synchronization. You can use one more FFs to make appropriate delays.

But best method is to redesign your existing design for synchronous logic and state machines. You can implemet very complex, fast and effective state machines with low CPLD resources.

Regards

 

[wjhzhx]

And another problem is when you use the same CPLD/FPGA but the faster, your CPLD/FPGA mayby not work.

 

[Hero]

Hi,

Even with same chip speed grades you will have propagation delay problems especially with FPGAs because delay times are very routing dependant.

So if make little modification you can expect significant delay changes.

Also asynchronous logic is very dependant on routing software which is not always predictable, sometimes very buggy and takes lot of time in complex cases with many time (delay) constrains.

For example I had a bad expiriences with only simple asynchronous SR latch. Compiler didn't optimize this latch and failed to fit design. When I used SR FF with fast clock instead latch compiler successfully fited design.

Recomendation never use asynchronous logic with FPGAs.

Regards