delay in verilog code

[neo_chip]

always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) cnt <= #1 {aw+1{1'b0}};
else
if(clr) cnt <= #1 {aw+1{1'b0}};
else
if( re & !we) cnt <= #1 cnt + { {aw{1'b1}}, 1'b1};
else
if(!re & we) cnt <= #1 cnt + { {aw{1'b0}}, 1'b1};

Hi everyone...........
this is a part of the code...........
why the "#1" delay is used for every assignment in the code..... whats the use.......

THNX

 

[agump]

In simulation , this delay will assure right schduling sequence. But I think this is not unnessary since today's cycel_based simulating tools can assure this even without these delay.On the other hand , this delay will increase your simulating time for the simulating tool must tackle these delay.

 

[stevepre]

another use is to have #1 delay so that the waveform display is easier to read.
but usually an experienced designer won't be confused by 0 delay waveform.

 

[xihushui]

use #1,i think the function is make you simulation near to the true condition.it is will ignored in synthesis

 

[funster]

this delay is to avoid potential clock skew or race condition or

hold time(for example, if register's output is output to a sdam model,

that will need hold time to be meet) problem in simulation.

best regards

always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) cnt <= #1 {aw+1{1'b0}};
else
if(clr) cnt <= #1 {aw+1{1'b0}};
else
if( re & !we) cnt <= #1 cnt + { {aw{1'b1}}, 1'b1};
else
if(!re & we) cnt <= #1 cnt + { {aw{1'b0}}, 1'b1};

Hi everyone...........
this is a part of the code...........
why the "#1" delay is used for every assignment in the code..... whats the use.......

THNX

 

[quan228228]

It is convenient for debug using debussy. Adding it or not will not affect simulation and systhsis.

I think it will not affect timing, including setup and hold timing. It just simulates the cell dalay.

 

[ray123]

We used this kind # delay is to avoid potential clock skew or race condition or
hold time at the i/o interface.