Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

decoupling capacitors to ground or supply voltage?

Status
Not open for further replies.

vaah

Member level 3
Member level 3
Joined
May 24, 2012
Messages
67
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
US
Activity points
1,785
Hi

Very basic question,

What power line do you connect your decoupling capacitor(s) to, ground or supply voltage?

For example, say I have a reference voltage (Vref) and want to stabilize the voltage using a bypass (decoupling) capacitors. What should I consider when connecting the other end of the capacitor to the power line?
 

Hi,

Connect the capacitor to the node where Vref is referenced to.
In most cases this is GND .... but not always.

Klaus
 

You should consider, from the recipient's "point of view"
what is the prime reference ground. If the "vref" is
developed against ground plane then the recipient ought
to use the same ground plane and any filtering also
returned to it.

When you get to remote or even differently-established
ground domains, it gets real messy.

In IC internal designs I have often "decoupled" bandgap
voltage reference nodes to local signal ground, and made
"images" sent up to the high side and then decoupled
there for high-side-referred voltage reference.

What makes the current loop (of the decoupling cap)
the shortest and least area?

What are the noise aggressor sources and how do they
relate to the input and ground paths, to be snubbed?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top