Decoupling capacitors in CMFB loop

[Chinmaye]

I have designed a fully differential 2 stage opamp with resistive CMFB circuit, to be used in switched capacitor amplifier. I see that, during the sampling phase, most of the times, the common mode output of the amplifier is moving towards the rails in the transient analysis while it is expected to be at 0V. Adding decoupling capacitors across the resistive CMFB helps but i still do not understand how the decoupling capacitors are able to maintain a common mode output of 0V. Can someone help me understand this?

 

[sutapanaki]

Hardly can someone help without schematic to look at and also simulation results.

 

[Chinmaye]

Hardly can someone help without schematic to look at and also simulation results.

I have attached the schematic and output waveforms from cadence. Note that the simulations are without the decoupling capacitors across the CMFB resistors. OP2 and ON2 are the single ended output waveforms of the switched capacitor amplifier using the 2 stage op-amp. OUT2 is the differential output OP2 - ON2. It can be seen that the output waveforms during the sample phase are close to the rails and not settling at 0V as expected. Adding a decoupling capacitor across all the 4 CMFB resistors solves the problem. But I am not sure how that solves the problem. As in, I am trying to analyse the theory behind that.

 

[sutapanaki]

Why are you saying that the common mode during sampling should be at 0V. Do you short the outputs to ground?
Maybe you don't have enough time for the common-mode to settle. Can you use lower frequency clock and see if it makes a change.

 

[Chinmaye]

Why are you saying that the common mode during sampling should be at 0V. Do you short the outputs to ground?
Maybe you don't have enough time for the common-mode to settle. Can you use lower frequency clock and see if it makes a change.

During the sample phase, the input is shorted to the output and the output common mode is maintained at 0V. The output is distorted at lower frequencies too.

 

[sutapanaki]

If I understand correctly, you short the input to output in a unity feedback configuration but you also short the inputs to ground or not?

 

[Chinmaye]

If I understand correctly, you short the input to output in a unity feedback configuration but you also short the inputs to ground or not?

The output is not explicitly shorted to ground. The output is suppose to stay at 0 due to the common mode feedback. Also, the decoupling capacitors bring this voltage to 0. But I am unable to understand why and how?

 

[sutapanaki]

From your explanation, what you are trying to do is something like this

The output common mode i a Vgs above ground. In this unity gain configuration the output common-mode voltage tries to be Vgs above ground because there is nothing that will pull the outputs to 0V. Because of the connection to the inputs, you will have Vgs across M1/M2 and the current source Iss. Which means the tail current source will most likely be in triode since it doesn't have sufficient headroom. So, the current in the diff pair reduces, maybe all the way to nothing. In this case the output common mode voltage will be at Vth of M7/M8. Question is, why do you think it is 0?

 

[Chinmaye]

From your explanation, what you are trying to do is something like this

View attachment 168536


The output common mode i a Vgs above ground. In this unity gain configuration the output common-mode voltage tries to be Vgs above ground because there is nothing that will pull the outputs to 0V. Because of the connection to the inputs, you will have Vgs across M1/M2 and the current source Iss. Which means the tail current source will most likely be in triode since it doesn't have sufficient headroom. So, the current in the diff pair reduces, maybe all the way to nothing. In this case the output common mode voltage will be at Vth of M7/M8. Question is, why do you think it is 0?

I have connected a current source at Q so that the current through the CMFB resistor R pulls down the voltage at the output to 0. Therefore the common mode output level is zero.

 

[sutapanaki]

OK, with this important piece of information, what I would suggest you to do is save the operating point at a time form you transient simulation where you think the common-mode is wrong, back-annotate it on the schematic and see what is pulling your voltage up.

Most probably, you try to pull down Q by a current source but this current goes through R3/R4 and they are high value resistors, so the voltage drop across makes Vout1/2 not 0, which perhaps doesn't turn off the input diff pair completely, so M5/M6 are still conducting current and compensate for the current at Q. This is just a speculation. Looking at the operating point from transient will show.

 

[Chinmaye]

OK, with this important piece of information, what I would suggest you to do is save the operating point at a time form you transient simulation where you think the common-mode is wrong, back-annotate it on the schematic and see what is pulling your voltage up.

Most probably, you try to pull down Q by a current source but this current goes through R3/R4 and they are high value resistors, so the voltage drop across makes Vout1/2 not 0, which perhaps doesn't turn off the input diff pair completely, so M5/M6 are still conducting current and compensate for the current at Q. This is just a speculation. Looking at the operating point from transient will show.

First of all, I apologise for the late reply. I ran the transient simulations and found that the current through the large resistors are very small and hence does not alter the Vout1 and Vout2. What I noticed is that, the inputs of the differential amplifier is going towards the rails during the sample phase, that is, when the inputs and outputs are shorted. Hence, the output is also going to the rails and getting saturated. Whereas, with decoupling capacitors, the input stays at CM 0V and hence allows the operation as expected.
I dont understand how connecting a decoupling capacitors hold CM 0V at the input. Is it something to do with the RC time constant?

 

[sutapanaki]

That's why in one of my previous comments I suggested to decrease the sampling frequency because it will show if the problem is related to the time constant. However, if the inputs/outputs are pulled up to the rails, instead of held at 0, there must be something pulling it. You have to find what is pulling it. This was the reason why I suggested annotating the operating point at that moment.

 

[Chinmaye]

That's why in one of my previous comments I suggested to decrease the sampling frequency because it will show if the problem is related to the time constant. However, if the inputs/outputs are pulled up to the rails, instead of held at 0, there must be something pulling it. You have to find what is pulling it. This was the reason why I suggested annotating the operating point at that moment.

I reduced the sampling frequency and ran a transient response. The behavior worsens as the sampling frequency decreases. I see that during the sample phase, the voltages are pulled up 0V initially as expected but the voltage is not staying at that point for long. The voltage stays at 0V for sometime and moves towards rails gradually. Putting a large capacitor at Q helps. Now, the next question I have is, Can the op-amp have 2 operating points to which it settles? Are there any tests to confirm this. Also, I am trying to find the the reason for the drift in voltage at Q. Thanks for the hint.

 

[sutapanaki]

Looks like you output voltage is not stable, so there is more there that's happening. So, if initially it is at 0V,then save the OP at that point and look at currents and voltages and see if it is what you expect. Then save another operating point when it drifts up towards rails. Try to find out what is causing the drift. It is most probably some current pulling it up.