fpga93
Newbie level 4
Hi all,
I am to design a DDR2 memory controller on Altera FPGA, but the ip core seems too complex with an extra PHY layer helping to interface with external memory device.I want to design a simple controller core based on an FSM. I want to know if thats possible without a PHY layer as Altera documentation states.If anyone has a previous experience in designing their own DDR2 mmwory controller ip core. Please do help.
Thanks,
fpga93
I am to design a DDR2 memory controller on Altera FPGA, but the ip core seems too complex with an extra PHY layer helping to interface with external memory device.I want to design a simple controller core based on an FSM. I want to know if thats possible without a PHY layer as Altera documentation states.If anyone has a previous experience in designing their own DDR2 mmwory controller ip core. Please do help.
Thanks,
fpga93