DDR DATA Sampling method

[nsgil85]

Hi,

If data is changing every clk event with DDR
What is the method of sampling DDR 8 bit parallel syncronic port (clk port = 150Mhz)


Thanks
Gil

 

[dpaul]

Assuming you are using Xilinx FPGA, an IDDR primitive can be used. It has 3 modes of operation and you can use any one of them as per your use. A lot depends what you want to do with the data after sampling it.

 

[nsgil85]

Hi,

Thanks for replay,
I'll use Stratix II for sampling,
the pourpes is to store pixels data with high frame rate, VGA size on SDRAM and to compose 6 small VGA frame on one HDMI 1080@60p.

Gil

 

[dpaul]

I don't work with Altera, but I think it is called ALTDDIO_IN.
Ok, you want to store this data, so I think you need to convert this to signal from DDR to SDR before feeding them to a FIFO.
Have fun!