DC-DC Converters or Charge Pumos

[praveen426]

Hello,

I am designing 10 Bit Successive approximation ADC at 0.4V in Cadence. However, my design is working perfectly at 1V.

I used DC-DC level converters but it is using 2 voltage supplies which is not desirable. I need only one supply i.e., 0.4V.

And now my question is how to get my supply voltage to 0.4V. I heard we can do it using Charge pumps.

Can anyone suggest me the design for charge pumps or DC-DC level converters or it would be great if anyone could provide me with shematics or any Journals

Thanks in advance.
Praveen.

 

[323e46]

You can use a CP to generate the higher voltage. However, you'll need a regulated 3x charge pump so you can get 1.2V off the 0.4V unregulated, and 1.0V regulated including switch losses etc. It would take area, as you need the switches and either on-chip capacitors (flying and reservoir) or external caps, so five pins (two each for the flying caps and one for the reservoir cap).

 

[praveen426]

Hey thanks mate...... I look into it and if i have any problem in designing I will get it back to you.

I really appreciate for your help....

 

[323e46]

no problem

 

[mtechvlsi]

i m designing on chip capacitive dc to dc converter.
plz help me with schmetic & layout.

 

[dick_freebird]

Since you have to drop voltage, and presumably aren't
drawing that much current, why not a simple LDO? You'll
get rid of a lot of on-chip switching noise that way.

As a practical matter, bring the LDO voltage out to a pin so
you can hang bulk decoupling on it, and/or force a voltage
if your regulator (of whatever form) happens not to work
exactly right.

 

[vani6]

I design on chip charge pump converter5 5 to 12 and I need schmatic and verilog code of charge pump. if u can than plz help me