dilan2005
Member level 4
hi,
i working on a project which takes input from cmos camera (ov7620) ,fed the data to the FPGA (spartan3E) and transmit data to the pc as UDP packet. in my first attempt i connect camera to the fpga by short wires about 15cm. the system work perfectly.
but when i increase the wire length about 60cm the image get distorted.
distorted in the sense the line alignment's were wrong.and some black and white pixels here and there in the image.
in ov7620 i use following lines.and connected to fpga using seperate ribbon cables. unfortunately i can remember the pixel clk rate but it should be bellow 27mhz.becasue it is the oscillator used on the cam.
cable1
=====
pxlclk
href
vsyc
--
--
--
+5v
gnd
cable2
====
Ydata[0]
ydata[1]
"
"
"
"
ydata[6]
ydata[7]
also i use resistor voltage devider to transfer 5v logic signals to 3.3v signals near the cmos camera.
following is the verilog code state machine which handle input form camera.
i also include the picture taken in two scenarios in the attachment. the frame in the left is the distorted one where i used 70cm ribbon cables and right frame is where i use 15cm ribbon cable.
any suggestion to tackle the problem please.
Thanks a lot!
regards
dilan[/code]
i working on a project which takes input from cmos camera (ov7620) ,fed the data to the FPGA (spartan3E) and transmit data to the pc as UDP packet. in my first attempt i connect camera to the fpga by short wires about 15cm. the system work perfectly.
but when i increase the wire length about 60cm the image get distorted.
distorted in the sense the line alignment's were wrong.and some black and white pixels here and there in the image.
in ov7620 i use following lines.and connected to fpga using seperate ribbon cables. unfortunately i can remember the pixel clk rate but it should be bellow 27mhz.becasue it is the oscillator used on the cam.
cable1
=====
pxlclk
href
vsyc
--
--
--
+5v
gnd
cable2
====
Ydata[0]
ydata[1]
"
"
"
"
ydata[6]
ydata[7]
also i use resistor voltage devider to transfer 5v logic signals to 3.3v signals near the cmos camera.
following is the verilog code state machine which handle input form camera.
Code:
always @(posedge pixelclk) begin
ledh<=href;
ledv<=vsync;
ybuf<=ydata;
case(state)
vsync_state:begin
if(vsync==1) state<=vsync_state; else begin state<=put_header; line_counter<=0 ;end
end
put_header:begin
wea1<=1;
dina1<=line_counter;
state<=put_data;
end
put_data: begin
if(href==1) begin dina1<=ybuf; state<=put_data;addra1<=addra1+1; end else begin wea1<=0; state<=setup_ready;end
end
setup_ready:begin
line_counter<=line_counter+1;
flip1<=~flip1;
if(flip1==1) begin
addra1<=11'h000;
image2ready<=1;
image1ready<=0;
end
else begin
addra1<=11'h300;
image2ready<=0;
image1ready<=1;
end
state<=href_zero;
end
href_zero:begin
if(vsync==1) state<=vsync_state; else begin
if(href==0) state<=href_zero; else state<=put_header;
end
end
endcase
end
i also include the picture taken in two scenarios in the attachment. the frame in the left is the distorted one where i used 70cm ribbon cables and right frame is where i use 15cm ribbon cable.
any suggestion to tackle the problem please.
Thanks a lot!
regards
dilan[/code]