data courroption problem from camera to the fpga

[dilan2005]

hi,
i working on a project which takes input from cmos camera (ov7620) ,fed the data to the FPGA (spartan3E) and transmit data to the pc as UDP packet. in my first attempt i connect camera to the fpga by short wires about 15cm. the system work perfectly.

but when i increase the wire length about 60cm the image get distorted.
distorted in the sense the line alignment's were wrong.and some black and white pixels here and there in the image.

in ov7620 i use following lines.and connected to fpga using seperate ribbon cables. unfortunately i can remember the pixel clk rate but it should be bellow 27mhz.becasue it is the oscillator used on the cam.

cable1
=====
pxlclk
href
vsyc
--
--
--
+5v
gnd


cable2
====

Ydata[0]
ydata[1]
"
"
"
"
ydata[6]
ydata[7]

also i use resistor voltage devider to transfer 5v logic signals to 3.3v signals near the cmos camera.

following is the verilog code state machine which handle input form camera.

always @(posedge pixelclk) begin
   
	 ledh<=href;
	 ledv<=vsync;
	 ybuf<=ydata;
case(state)
vsync_state:begin
				if(vsync==1) state<=vsync_state; else begin state<=put_header; line_counter<=0 ;end
				end

put_header:begin
           wea1<=1;
			  dina1<=line_counter;
			  state<=put_data;
			  end
put_data: begin
			 if(href==1) begin dina1<=ybuf; state<=put_data;addra1<=addra1+1; end else begin wea1<=0; state<=setup_ready;end
		    end
setup_ready:begin
				line_counter<=line_counter+1;
				flip1<=~flip1;
					if(flip1==1) begin     
						addra1<=11'h000;
						image2ready<=1;
						image1ready<=0;
						
					end
					else  begin
						addra1<=11'h300;
						image2ready<=0;
						image1ready<=1;
					end 
				state<=href_zero;
			   end
href_zero:begin
				if(vsync==1) state<=vsync_state; else begin
																 if(href==0) state<=href_zero; else state<=put_header;
																 end
			 end
endcase
	
end

i also include the picture taken in two scenarios in the attachment. the frame in the left is the distorted one where i used 70cm ribbon cables and right frame is where i use 15cm ribbon cable.

any suggestion to tackle the problem please.

Thanks a lot!

regards
dilan[/code]

 

[FvM]

Does your wiring table mean, you have no signal ground with the second cable and a single ground line with the first? I can't imagine how this should work with a 70 cm cable!

You can retry with a scheme that uses a ground for each signal as with a parallel harddisk (PATA) interface. Also dimensioning of the voltage divider should be choosen to achieve damping of line pulse reflections. Alternatively, a combination of a source side serial termination and a pulldown resistor at the FPGA that sets a suitable high level could give better signal quality.

I haven't seen a specification of the camera chip that includes a specification of digital output (except output voltage). It may be in doubt, if the chip is able to drive a cable without a buffer. At least empirical optimization of termination parameters may be necessary.

 

[dilan2005]

hi,

thanks FVM ! i am undergraduate ,i am totally new to this kind of stuff, is there any sort of guides (ebooks,links,white papers)that i could follow to know more about these issues and how to solve those practically.

thanks a lot!

rgds
dilan

 

[FvM]

I think, it's promising generally, that you succeeded in transmitting and acquiring the image to the FPGA. This demonstrates your ability of basically facing the challenge.

The first suggestion is of course to keep the digital data cabling as short as possible (the application may require a certain length, however).Using a flat cable isn't bad, but you should have some more ground wires, up to possibly one ground wire for each high speed signal This may be already sufficient to solve the issues. It would be helpful if you can check the signal waveforms with an oscilloscope, although usual passive probes distort the signals due to capacitive load. But it's an important tool to optimize e. g. termination resistors and find the cause for transmission errors.

Understanding the said transmission problems and possible solutions, to my opinion is centered around understanding the properties of transmission lines in pulse transmission and basic effects as reflections, termination and impedance matching. There are many introductions to high speed electronics dealing with this topics, but I find it difficult to give a particular suggestion. May be other forum members can.

 

[dilan2005]

hi FvM
i do some experiments with the setup.it seems to me that the pxlclk,vsync,href lines get distroted and y data lines not effected very much.

so i think i must concentrate on these clk signals rather than data signals because in negative the y data is setup and by the positive edge of pixel clk the signals should be stable.

i try to solve problem by using grounding lines in following pattern

+5v
gnd
pixelclk
gnd
vsync
gnd
hreg
gnd


but it doesn't seems to work.i feel that more capacitance will be added to the line and Z0 will get lower and difficult match.

i am thinking of doing some impedance matching.
my problem is normally we do impedance matching to impedance known cables like 75ohm,50ohm coaxial cables.how could i find out the impedance of the flat cables.is there any other easy practical way!

source side serial termination and a pulldown resistor

can u please explain more about this.or a suitable link

It may be in doubt, if the chip is able to drive a cable without a buffer

is this means that the signal strength is not enough! or some thing regarding impedance!


Thanks a lot!
rgds
dilan[/quote]

 

[imag3ne]

I've got same problem how to connect ov7620 to fpga and to lcd .. have someone some solution ... please can you sent me to diro85@gmail.com
thanks a lot