Current Steering DAC layout, placement and floor planning

[raduga_in]

dac layout

Hi guys !!

At present I am designing a 12-bit Current Steering DAC at 500MHz clock.
It is segmented as 4-bits binary and 8 bits thermometric. I am a bit
confused about it's layout and floor-planning. I would really appreciate if some
of you can help me out with some references and layout images ..

TIA

Raduga

 

[raduga_in]

current steering dac layout

Guys! help me !!

Raduga

 

[ashik_na]

I am also needed this plz help us.....

 

[nkzz]

Re: Current Steering DAC layout, placement and floor plannin

i am also designing current steering dac.
maybe we can discuss this topic if you like.
msn:tjfznk@hotmail.com