Current sources within a differential cascoded structure

[Hawaslsh]

Hello all,
I am working through some lectures on CMOS analog design and I saw something that wasn't fully explained (or, more likely, I missed it). Above is very simple NMOS differential pair with real resistors as their load, Rd. In this case, the bias current is easily set by a single current source.

However, to increase the gain, we replaced the load resistors, with an ideal current source (pink) or a cascode current source (blue). In this case, clearly Iss still represents the total bias current, but if there is bad design can't the 3 different current sources "fight" each other? For example, if Iss is designed to sink 1mA, but we poorly designed the load current sources to source .6mA, what would happen? In all the calculations we did, we assumed Iss = (ideal current source *2). Is that a valid assumption or are we assuming it design correctly biased to source 0.5mA from each source and sink 1mA from Iss?
Sorry for the short explanation/question. The kids just got back home,
Happy to provide more context,
thanks in advance!

 

[BradtheRad]

Yes, it's expected that multiple current sources lead to 'fighting', if that's the focus of your question.

As for the long-tail pair, it's true even with just one current source (that is, tail current in the basic configuration), the differential detection operates by means of the left column 'grabbing' more current than the right column. (Or else vice versa.)
In the event of equal bias inputs, then the columns conduct equally.

Overall behavior is similar to a Wheatstone bridge which is a simpler form of differential detector.