preethi19
Full Member level 5
Hi i am just starting to learn about layout design. I am trying to do the layout for a circuit. In the schematic i have run the simulation using a current source. The current source positive is given to the gate of a nmos and the -ve terminal of the current source is connected to vdd or can be grounded. So when it comes to layout how am i supposed to do this. Should i just leave the gate of the transistor as an input pin? so wer the current source can be connected to that pin separately. And for the negative terminal which i can connect to vdd or gnd should i leave any space for that. I'm doing my layout using cadence. Thank you!!!