Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Go to Silicon Integration Initiative (Si2), http://www.si2.org/
-------------------------------------------------------------------------
LEF DEF Format Specification **broken link removed**
hi,
what you want is a whole flow.
you have to p&r your design and generate gds, and then suing abstract from c@dence to extract lef file.
or you can use encounter or astro to extract lef,but accuracy is a matter.
hi linuxluo,
yes, i agree with you about creating lef. this is almost like backtracking. What i was thinking was, along with the netlist, if it has memories, then, a lef will be given so that the memory can be made into a blackbox in the netlist during the semi-custom flow. my question is:
do you take the memory's netlist alone through the complete flow and generate the lef file?
in this way, can we generate the physical information of the memory and create a blackbox that can be used along with other netlists ??
Hope i'm clear. Incase if i'm not please let me know.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.