matrixofdynamism
Advanced Member level 2
What is the simplest way to record signals using an oscilloscope or logic analyzer and then use them to create test vectors for a VHDL/Verilog design?
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What is the simplest way to record signals using an oscilloscope or logic analyzer and then use them to create test vectors for a VHDL/Verilog design?
can your scope dump information into a file (CSV-like, maybe?) ? I would write a testbench that parses the scope output file and makes a simulation environment out of it.