Create or Generation of I/O PADs

[Kulprashant]

Hi all,
I am working on flooorplaning & powerplanning using SoC Encounter tool.
in powerplanning how to generate I/O PADS and when these i/o pads r required(does this i/o pads required when anlog block is present in the design) and what basis i have to choose number of power stripe & rings.
plz suggest me.

Thanks & Regards,

Prashant

 

[anjali]

To calculate width of power rings,

width of power ring on one side = (total current passed to the chip / metal density) / 4

divide by 4, on the assumption that all sides of the chip requires same current density.

Added after 25 seconds:


To calculate width of power rings,

width of power ring on one side = (total current passed to the chip / metal density) / 4

divide by 4, on the assumption that all sides of the chip requires same current density.

 

[tarkyss]

you want to generate IO by youself?
normally it is provided by foundry, if you want to creat io pad by youself, you must to do lots of work, for example. detemine esd protection structure, layout, simulation, rc extraction, lib generate, esd test and so on

 

[p_shinde]

then this I/O pads doesnt depend on the ciruitry which we are going to put on the core???

for a certain technology same I/O pads can be used for different chips???????


Thanks,
Prasad

 

[shankarmit]

Io pads are required when u are desing a chip that is going to fabricated as top level.. otherwise macro dont need io pads
Its nothing depends on anolog blocks present or not..

Its depends on where is pin is real outpin of you chip.. if the pin is real pinof chip then io pads are necessary.. dont get confused.. some times this pins are connected to another module when u use this module as macro...

Power strap and width calculation see below link

www.vlsitechnology.org in that click on IR drop summary..

Regards
Shankar