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Normally we design the FPGA or CPLD in synchronized way. In other words, we should buffer the data or the control signal. If the delay is larger than the cycle of the clock, the signal may be triggered in a wrong way. So the delay is very important to evalute the max freqency of the chip.
Suppose you have a device, connected to the CPLD input. The device, on a clock edge, output the data to the CPLD.
Now, that same clock is used by the CPLD. The CPLD must have time to process the data at input, and set the correct result at the input of it's output registers, *before* the next clock edge.
There's 2 main things involved here. First, when the first clock edge occur, and the device send the new data to the CPLD, there's a small delay between clock edge, and valid data. Next, there's a delay needed by the CPLD to evaluate those data, and produce correct result.
Only when the result is currectly evaluated, may the next clock edge occur (where those resulting data get shifted into the CPLD flip-flop).
So, the max clock frequency depend on
- The CPLD speed grade (how fast it can evaluate expressions, by it's logic block).
- The delay between clock edge and the time at which data is valid at CPLD input pins. This can be told to the synthesizer and P&R with parameters.
The output delay can also be specified, so the 'compiler' can minimize output delay to the next chip.
All of this affect the maximum frequency on the CPLD.
It also depends on your vhdl code !
for the same chip and same needed functions , different codes reflects on maximum frequency (i.e. using one clock edge or both and so on..)
This can be easily shown from the synthesis report
There are multiple factors that decide your maximum frequency such as logic complexity, level of register, and the density of your design. In general, it is recommended to limit your logic density to 75% of the total LE. According to xilinx's datasheet, coolrunner 2 can go up to 333MHz. Anyway, don't think about you can make a 333MHz design using coolrunner 2.
It also depends on your vhdl code !
for the same chip and same needed functions , different codes reflects on maximum frequency (i.e. using one clock edge or both and so on..)
This can be easily shown from the synthesis report
Yes!
I have two design 64 bit up counter
1) 304,04 MHz clock (LPM function with Look-ahead approach to counter design)
2) 137,65 MHz clock (LPM function only)
I'm kind of newbie to this but if you have a schematic or a vhdl code, after simulation the (let's say Xilinx Foundation) software will tell the maximum frequency and a lot of other delays...
the upper frequency is deterimed by key transport path. why? because, if you input new data but old data has not been sent out, so in some palce the time relation does not meet. To increase your upper frequency you can use pipeline.
It also depends on your vhdl code !
for the same chip and same needed functions , different codes reflects on maximum frequency (i.e. using one clock edge or both and so on..)
This can be easily shown from the synthesis report
how to improve the maximum frequency?
first,through change the route to reduce the delay
second,reduce the inputs of the combination logic
circuit(because the basic structure of fpga is lut,it
has 4 inputs.if we use lots of inputs,it will bring
cascade delay.)
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